Methods for efficient use of Lagrangian relaxation for SOC soft-module floorplanning

In this paper, we present new methods to improve the performance of sequence-pair-based floorplanning algorithms for SOCs (system-on-chip) and microprocessors. Edge pruning and more accurate initial value settings significantly reduce CPU time for soft-module floorplanning of large numbers of modules using Lagrangian relaxation (LR). A floor planner, ELF-SP, which implements these methods, runs faster than published approaches, and produces better or comparable floorplans.