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A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques
- Source :
- IEEE Journal of Solid-State Circuits. 50:1945-1959
- Publication Year :
- 2015
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2015.
-
Abstract
- The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.
Details
- ISSN :
- 1558173X and 00189200
- Volume :
- 50
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........bd3ecdd5a1b8474a68f8bb2d19ea9028