An Application of System Level Efficient ESD Design for HighSpeed USB3.x Interface

Authors :: Jianchi Zhou
Giorgi Maghlakelidze
Harald Gossner
David Pommerenke
Pengyu Wei
Source :: 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
Publication Year :: 2018
Publisher :: IEEE, 2018.
Abstract: A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation.

Subjects :: 010302 applied physics
Electrostatic discharge
Computer science
Interface (computing)
020206 networking & telecommunications
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
01 natural sciences
0103 physical sciences
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
System level
Current (fluid)
Hidden Markov model
Hardware_LOGICDESIGN
Voltage

Database :: OpenAIRE
Journal :: 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)
Accession number :: edsair.doi...........bd0a0e5ddb956dbaa2e0a950f8f9451d
Full Text :: https://doi.org/10.23919/eos/esd.2018.8509765

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