Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Adaptive artificial neural network (ANN)-coupled low-density parity-check (LDPC) error-correcting code (ECC) (ANN-LDPC ECC) is proposed to increase acceptable errors for various NAND flash memories. The proposed ANN-LDPC ECC can be the universal solutions for 3-D and 2-D, charge-trap and floating-gate NAND flash memories. In 3-D NAND flash, lateral charge migration, vertical charge de-trap, inter floating-gate capacitive coupling noise, and inter word-line variations cause errors. On the other hand, in 2-D NAND flash, the charge de-trap and the harsh inter floating-gate capacitive coupling of adjacent word-lines and bit-lines cause errors. To solve these reliability problems, the proposed ANN automatically and adaptively compensates for complex memory cell errors. Moreover, the proposed ANN-LDPC can reproduce the dynamic endurance and data-retention time dependence of errors. In addition, this paper evaluates the impacts of the chip-to-chip variations on the proposed ANN-LDPC. The proposed ANN-LDPC is implemented in the storage controller and can precisely and adaptively estimate bit-error rate (BER) and log-likelihood ratio (LLR). By using the precise LLR, LDPC decoder effectively corrects errors. As a result, ANN-LDPC extends the acceptable data-retention time by over 76 $\times $ and 45 $\times $ compared with conventional Bose–Chaudhuri–Hocquenghem (BCH) ECC in 3-D and 2-D triple-level cell (TLC) NAND flash memories, respectively.