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Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration

Authors :
Balasubramanian S. Pranatharthi Haran
B. Peethala
Kedari Matam
Kisik Choi
Nicholas A. Lanzillo
J. Casey
L. Chang
Terry A. Spooner
D. Janes
David L. Rath
Benjamin D. Briggs
Donald F. Canaperi
M. Packiam
Devika Sil
Hosadurga Shobha
Ryan Kevin J
Source :
2021 IEEE International Interconnect Technology Conference (IITC).
Publication Year :
2021
Publisher :
IEEE, 2021.

Abstract

The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.

Details

Database :
OpenAIRE
Journal :
2021 IEEE International Interconnect Technology Conference (IITC)
Accession number :
edsair.doi...........b62de6222fd8be5e825a22aeea8b864c
Full Text :
https://doi.org/10.1109/iitc51362.2021.9537484