Thin film backside gettering in n-type (100) Czochralski silicon during simulated CMOS process cycles

The gettering effectiveness of various backside gettered polysilicon, silicon nitride, or poly + nitride film structures on n-type (100) Czochralski silicon wafers from a single ingot during simulated complementary-metal-oxide-semiconductor process cycles has been investigated by synchrotron section topography, breakdown voltage of 25-nm gate oxide, and minority carrier lifetime measurements. Interfacial structure was studied by cross-section transmission electron microscopy. Our studies show that for successful implementation of thin film backside gettering, good control of interactions between intrinsic gettering and thin film backside gettering during device processing cycles is critical. Thin film deposition generally increases oxygen precipitation. No extended defects propagate toward the bulk silicon. The structural and electrical quality of a denuded zone is found important. The best device yield (90%) is observed from the middle section wafers (with a 2 μm thick polysilicon backsurface coverage) which develop no recognizable bulk precipitates and stacking faults after the complete thermal cycles.