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A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator

Authors :
Hiroshi Shiroshita
Sachiya Tanaka
Yuki Yagishita
Hiroki Kihara
Toshiyuki Ogata
Hiroaki Hayashi
Kenichi Maruko
Kenji Konda
Tatsuya Sugioka
Takayuki Aoki
Masahiro Sato
Taichi Niki
Hironobu Konishi
Yasunori Tsukuda
Zhiwei Zhou
Hisashi Owa
Takeshi Ogura
Source :
ISSCC
Publication Year :
2010
Publisher :
IEEE, 2010.

Abstract

Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].

Details

Database :
OpenAIRE
Journal :
2010 IEEE International Solid-State Circuits Conference - (ISSCC)
Accession number :
edsair.doi...........b23ccf96703ac04300720a67b27dfd3f