Hardware/software co-design of Dynamic Binary Translation in X86 emulation

X86 emulation is an effectively method to solve the problem of software compatible between X86 and RISC processors, such as ARM, PowerPC, Alpha and so on. Dynamic Binary Translation (DBT) in X86 emulation translates the X86 binary codes to RISC binary code dynamically so that the software based on X86 platform could execute undifferentiated on RISC platform. However, the DBT based on software is one of the performance bottlenecks nowadays. In this case, this paper discusses a new method for DBT with hardware/software co-design. A hardware unit is designed to accelerate the DBT system, including Instruction Decoder, RISC Code Table, Translation Cache and Cache Query Unit. Instruction Decoder analyses the meaning of X86 binary codes and then looks up RISC Code Table to obtain the corresponding RISC binary codes. Translation Cache stores the recently translated RISC binary codes to reduce the repeated instruction translation. Cache Query Unit is used to determine whether cache hit or not. Finally, we achieve the hardware unit using Verilog HDL. Experiment showed that the co-design DBT system could work accurately.