FPGA-Based Implementation of an Event-Driven Spiking Multi-Kernel Convolution Architecture

This brief presents an event-driven spiking multi-kernel convolution architecture for processing address-event representation (AER) streams from dynamic vision sensor (DVS) chips. The processor architecture is designed based on leaky integrate-and-fire (LIF) neural model, and employs pipeline scheme to accelerate data processing. A new scheme for arranging neuron membrane potentials and kernels in memories is proposed, which enables row-by-row kernel processing and accelerates the multi-kernel convolution computation. An FPGA prototype of the proposed architecture is implemented on a Xilinx Zynq FPGA development board with 100 MHz clock frequency. The proposed processor architecture computes 64 filters with configurable kernel size (from 1x1 to 32x32) on input flow, obtaining the latency of 0.10 us to 10.33 us for convoluting an event, and the energy of 0.12 nJ and 12.08 nJ per event per convolution, respectively.