Strained-Si channel heterojunction p-MOSFETs

A simulation study of a short-channel strained-Si p-MOSFET is presented. An analytical model for hole mobility enhancement in strained silicon has been used in a two-dimensional (2D) device simulator to evaluate the strain dependence of the drain current and transconductance. Simulation results have been verified with experimental device results and the leverage of the strained-Si channel p-MOSFET over conventional Si p-MOSFETs is shown both at low temperature and room temperature. Optimal confinement of holes within the strained silicon occurs for a graded Si 0.7 Ge 0.3 buffer cap thickness of 40 nm. This layer structure gives rise to an enhancement in transconductance of up to 60%.