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Generation of a multilevel SPWM technique of 3, 9 and 21 levels with FPGAs

Authors :
N. M. Salgado-Herrera
J.R. Rodriguez-Rodriguez
Antonio Ramos-Paz
Aurelio Medina-Rios
Source :
2013 North American Power Symposium (NAPS).
Publication Year :
2013
Publisher :
IEEE, 2013.

Abstract

This paper deals with the implementation of parallel processing SPWM multilevel techniques through programmable gate arrays (Field Programmable Gate Arrays, FPGAs). It is shown that switching losses in power converters significantly decreases with an increased number of levels in the SPWM signal, thus providing an efficient energy transfer. The multilevel SPWM control response of 3, 9 and 21 levels in VHDL through the FPGA Xilinx Spartan family is illustrated.

Details

Database :
OpenAIRE
Journal :
2013 North American Power Symposium (NAPS)
Accession number :
edsair.doi...........aac0a3962af3f5d0a1d0b68afc718080
Full Text :
https://doi.org/10.1109/naps.2013.6666843