Ultra-high-performance 0.13-μm embedded DRAM technology using TiN/HfO/sub 2//TiN/W capacitor and body-slightly-tied SOI

We present an ultra-high-performance 0.13-/spl mu/m embedded DRAM technology, which improves transistor performance in both logic devices and DRAM cells. Simulation results indicate that the typical random access cycle of a 16-Mbit DRAM core exceeds 570 MHz. The full-metal DRAM structure having a newly developed TiN/HfO/sub 2//TiN/W capacitor minimizes the aspect ratio of the cylindrical capacitor electrode to reduce contact resistance in the logic area. Integration of the embedded DRAM with BSTSOI (Body-Slightly-Tied SOI) is also demonstrated, with which the logic performance can be further improved and the DRAM cell area is free from floating-body effects.