A hierarchical defect repair approach for hybrid nano/CMOS memory reliability enhancement

Due to the small size of nanoscale devices, they are highly prone to process disturbances which results in manufacturing defects. Some of the defects are randomly distributed throughout the nanodevice layer. Other disturbances tend to be local and lead to cluster defects caused by factors such as layer misalignments, line width variations and contamination particles. In this paper, initially a method is proposed for separately identifying cluster defects from random ones. Subsequently a hardware repair structure is presented to repair the cluster defects with rectangular window transfer vectors using a range-matching content addressable memory (RM-CAM) and random defects using defect aware triple-modular redundancy (DA-TMR) columns. It is shown that a combination of these two approaches is more effective for repairing defects at higher error rates with an acceptable overhead. The effectiveness of the technique is shown by examining defect recovery results for different fault distribution scenarios. Also the mapping circuit hardware performance parameters are presented for various memory sizes and the speed, power dissipation and overhead factors are reported.