A Boundary-Scan Based On-Line Circuit Performance Monitoring Scheme

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.