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A Boundary-Scan Based On-Line Circuit Performance Monitoring Scheme
- Source :
- Journal of the Institute of Electronics and Information Engineers. 53:51-58
- Publication Year :
- 2016
- Publisher :
- The Institute of Electronics Engineers of Korea, 2016.
-
Abstract
- As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.
- Subjects :
- Scheme (programming language)
Boundary scan
Circuit performance
Semiconductor technology
Computer science
Controller (computing)
Real-time computing
02 engineering and technology
Line (electrical engineering)
020202 computer hardware & architecture
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
computer
computer.programming_language
System error
Degradation (telecommunications)
Subjects
Details
- ISSN :
- 22875026
- Volume :
- 53
- Database :
- OpenAIRE
- Journal :
- Journal of the Institute of Electronics and Information Engineers
- Accession number :
- edsair.doi...........a63a421b8d53da2195a4a4431ad38c33