A cost effective 2-D adaptive block size IDCT architecture for HEVC standard

High Efficiency Video Coding (HEVC) is the currently developing video coding standard by the MPEG and ITU organizations. Unlike previous video codec standards, HEVC employs variable block size integer DCT/IDCT to conduct spatial redundancy compression. In this paper, a novel 2-D IDCT VLSI architecture for HEVC standard is presented. Using adaptive block size scheduling scheme, the proposed architecture supports variable block size IDCT from 4×4 to 32×32 pixels with low hardware overhead while keeping the highest performance. Using TSMC 65nm 1P9M technology, the synthesis result shows that the 2-D architecture achieves the maximum work frequency at 400MHz and the hardware cost is about 112.5K Gates. Experimental results show that the proposed architecture is able to deal with real-time adaptive HEVC IDCT of 4K×2K (4096×2048)@30fps video sequence at 179.4MHz. In consequence, it offers a cost-effective solution for the future UHD applications.