Back to Search Start Over

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

Authors :
Hiroshi Ueda
Keiji Matsumoto
Hiromi Watanabe
Shinichi Yoshioka
Katsuji Takakubo
Kenichi Iwata
Takahiro Irita
Seiji Mochizuki
Jun Takemura
Motoki Kimura
Eiji Yamamoto
Toshihiro Hattori
Masakazu Ehama
Tadashi Teranuma
Source :
IEEE Journal of Solid-State Circuits. 45:59-68
Publication Year :
2010
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2010.

Abstract

A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm2 die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.

Details

ISSN :
1558173X and 00189200
Volume :
45
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........9eb54ad2acdd416881d70c1b41a908fd
Full Text :
https://doi.org/10.1109/jssc.2009.2031797