A new methodology for assessment of the susceptibility to data retention in floating gate non-volatile memories

We have developed a new methodology with statistical simulation of leakage current resulting in V t shift over time of tail bit for assessment of the susceptibility to data retention in floating gate flash memories. The statistical simulation results of V t distribution are verified with measurements of programmed bit in actual product with good agreement. The new methodology can effectively predict the V t distribution of programmed bit for determining the data retention failure rate of floating gate non-volatile memories without multi-year bakes and analyzing the leakage mechanism of concern for our process and design.