A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.