Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process

Leakage power reduction techniques are crucial for energy-efficient circuits. This paper investigates the leakage suppression capability, performance, and reliability of dynamic leakage suppression logic (DLSL) and feedforward leakage self-suppression logic (FLSL) techniques, crossing different technology nodes from TSMC 180 nm bulk CMOS to 7 nm FinFET Plus process. Compared with CMOS benchmarks, experimental results show that DLSL-based benchmarks demonstrate a leakage power reduction for four orders of magnitude in 180 nm and 130 nm technologies, while only two orders of magnitude in other technologies. Moreover, FLSL offers a 4-28× performance improvement over DLSL at a cost of 2× leakage power.