Simulation of residual stress and its impact on a poly-silicon channel for three-dimensional, stacked, vertical-NAND flash memories

In this work, we present the results of an investigation of the impact of the stress on a poly-silicon channel induced by the neighboring layers in three-dimensional vertical NAND (3D V-NAND) flash memories. Using 3D process simulations, we confirmed the distributions of the residual stress after each process step in the cross-section of a NAND flash unit cell. To investigate the impact of the stress on the poly-silicon channel, we also studied the residual stress after changing the intrinsic stresses of the oxide-nitride-oxide (ONO) layer and the tungsten layer used as a gate. We found that the amplitude of the residual stress in the applied layer became larger as the intrinsic stress increased. In addition, the intrinsic tensile/compressive stresses in the outer layers affected the residual stresses of the previously deposited layers in an opposite nature of the stresses. The cylindrical poly-silicon channel was influenced by the intrinsic stresses of the oxide layers adjacent to the nitride and the tungsten films, with the intrinsic stress of the tunnel oxide having the greater effect on the residual stress in the channel. Because such stresses affect the electrical properties of the devices, optimized deposition conditions are required to control them. Such conditions would aid in improving the performances of 3D NAND flash memories.