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RMS-TM

Authors :
Mateo Valero
Osman Unsal
Adrian Cristal
Ibrahim Hur
Gokcen Kestor
Vasileios Karakostas
Source :
ACM SIGMETRICS Performance Evaluation Review. 39:19-19
Publication Year :
2011
Publisher :
Association for Computing Machinery (ACM), 2011.

Abstract

Transactional Memory (TM) has been proposed as an alternative concurrency mechanism for the shared memory parallel programming model. Its main goal is to make parallel programming for Chip Multiprocessors (CMPs) easier than using the traditional lock synchronization constructs, without compromising the performance and the scalability. This topic has received substantial research attention and several TM designs have been proposed using various TM benchmarks. We believe that the evaluation of TM proposals would be more solid if it included realistic applications, that address on-going TM research issues, and that provide the potential for straightforward comparison against locks. In this paper, we introduce RMS-TM, a Transactional Memory benchmark suite composed of seven real-world applications from the Recognition, Mining and Synthesis (RMS) domain. In addition to featuring current TM research issues such as nesting and I/O and system calls inside transactions, the RMS-TM applications also provide a mix of short and long transactions with small/large read and write sets with low/medium/high contention rates. These characteristics, as well as providing lock-based versions of the applications, make RMS-TM a useful TM tool. Current TM benchmarks do not explore all these features. In our evaluation with selected STM and HTM systems, we find that our benchmark suite is also scalable, which is useful for evaluating TM designs on high core counts.

Details

ISSN :
01635999
Volume :
39
Database :
OpenAIRE
Journal :
ACM SIGMETRICS Performance Evaluation Review
Accession number :
edsair.doi...........997e60891c5649dd3d4d019917db488c
Full Text :
https://doi.org/10.1145/2160803.2160840