29.3 Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting

There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically-time-varying (LPTV) circuits [1], [5]. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, insertion loss (IL), and chip area to become compelling when compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD) [6]. This paper introduces three innovations - (i) a switched-capacitor clock-boosting scheme, (ii) high-Bragg-frequency quasi-distributed T-lines based on periodically loaded inductors, and (iii) a gyrator based on switched partially reflecting T-lines - that enable such a leap for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1GHz 0.18µm SOI CMOS circulator that exhibits 2.1/2.6dB TX-ANT/ANT-RX IL (0.3dB better than prior art [4]), +34dBm TX-ANT P1dB (2.5x or 4dB better), and 40% lower chip area, all at 39mW power consumption (4.4x lower).