Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime

MLA

Mariko Takayanagi, et al. “Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime.” IEEE Transactions on Electron Devices, vol. 58, Apr. 2011, pp. 996–1005. EBSCOhost, https://doi.org/10.1109/ted.2011.2106786.

APA

Mariko Takayanagi, John Bruley, K. Ariyoshi, Ryosuke Iijima, Lisa F. Edge, & Vamsi Paruchuri. (2011). Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime. IEEE Transactions on Electron Devices, 58, 996–1005. https://doi.org/10.1109/ted.2011.2106786

Chicago

Mariko Takayanagi, John Bruley, K. Ariyoshi, Ryosuke Iijima, Lisa F. Edge, and Vamsi Paruchuri. 2011. “Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime.” IEEE Transactions on Electron Devices 58 (April): 996–1005. doi:10.1109/ted.2011.2106786.