Technology, CAD tools, and designs for emerging 3D integration technology

Because of continued advancements in process technology, three-dimensional (3D) integration with stacked chips is emerging as a promising solution to meet the challenges of high-performance, differentiated technology integration, and smaller form factor in complex System-on-a-Chip (SoC) design. High density vertical connections between stacked strata reduce well-known interconnect delay issues and increases interconnect bandwidth in a 3D chip. Adding the third dimension to design opens up new opportunities for EDA tools and design/architectural techniques to fully explore new approaches and address the challenges of 3D integration.This tutorial will discuss following key topics in 3D integration: -Overview of 3D integration process: Through-Si via, die-on-wafer, wafer-on-wafer bonding -Market applications and drivers for 3D integration -Design techniques for cost-effective 3D integration: 3D IP reuse, design-for-test -Thermal issues in 3D -CAD tools and algorithms for 3D IC design -3D microprocessor design -3D multi-core architectures with network-on-chip