Cite
CMOS shallow trench isolation x-stress effect on channel width for 130nm technology
MLA
P. B. Y. Tan, et al. “CMOS Shallow Trench Isolation X-Stress Effect on Channel Width for 130nm Technology.” 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Jan. 2006. EBSCOhost, https://doi.org/10.1109/icsict.2006.306306.
APA
P. B. Y. Tan, A.V. Kordesch, & Othman Sidek. (2006). CMOS shallow trench isolation x-stress effect on channel width for 130nm technology. 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. https://doi.org/10.1109/icsict.2006.306306
Chicago
P. B. Y. Tan, A.V. Kordesch, and Othman Sidek. 2006. “CMOS Shallow Trench Isolation X-Stress Effect on Channel Width for 130nm Technology.” 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, January. doi:10.1109/icsict.2006.306306.