A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors

MLA

Yasunobu Nakase, et al. “A Wide Range 1.0 V-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors.” 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), Mar. 2004. EBSCOhost, https://doi.org/10.1109/vlsic.2003.1221216.

APA

Yasunobu Nakase, T. Shimada, S. Iwade, Hiromi Notani, & H. Makino. (2004). A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors. 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408). https://doi.org/10.1109/vlsic.2003.1221216

Chicago

Yasunobu Nakase, T. Shimada, S. Iwade, Hiromi Notani, and H. Makino. 2004. “A Wide Range 1.0 V-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors.” 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), March. doi:10.1109/vlsic.2003.1221216.