A 0.1–5GHz flexible SDR receiver in 65nm CMOS

A 0.1–5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6–47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30–40dB rejection improvement by calibration.