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32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3

Authors :
D. Galpin
Alexis Farcy
E. Richard
P. Brun
G. Imbert
Jonathan Pradelles
Vincent Jousseaume
M. Assous
B. Icard
Daniel Barbier
C. Jayet
C. Monget
Sonarith Chhun
Michel Haond
Sylvain Maitrejean
Vincent Arnal
J. Guillan
S. Manakli
K. Hamioud
Aziz Zenasni
Source :
Microelectronic Engineering. 87:316-320
Publication Year :
2010
Publisher :
Elsevier BV, 2010.

Abstract

A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k=2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k=2.3 is investigated using a multi-level metallization test vehicle in a 45nm mature generation.

Details

ISSN :
01679317
Volume :
87
Database :
OpenAIRE
Journal :
Microelectronic Engineering
Accession number :
edsair.doi...........8e61fa6273f887f806348d3683ae5ac2
Full Text :
https://doi.org/10.1016/j.mee.2009.07.008