A 3-D Reconfigurable Memory I/O Interface Using a Quad-Band Interconnect

This article presents a 3-D reconfigurable memory I/O transceiver using a quad-band interconnect (QBI). The 3-D QBI provides I/O data reconfigurability, decreases latency, and reduces pin count for future compact mobile memory interfaces. The 3-D integrated circuit (3-D IC) technique is utilized to reduce signal latency and improve signal integrity. A novel quad-band transformer is proposed to achieve reconfigurable four-band data communication and reduce the I/O pin count by four times. A two-tier QBI die-stack is implemented to verify the QBI design. Face-to-face configuration with $\mu $ bump interconnects is used to save cost. The QBI chips are designed and fabricated in a 180-nm CMOS process. The chip areas of the top and bottom dies are 1.77 and 1.4 mm2, respectively. The measured data rates, with bit error rate (BER) $ , are up to 2 Gb/s in the baseband (BB) and 2.3, 2.5, and 3 Gb/s in RF-bands. The QBI energy efficiencies, with a 1.8-V supply voltage, are 5.9 pJ/b in the BB and 6.2, 7.4, and 8 pJ/b in the RF-bands.