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FinFET and Nanowire-FET Device Design and Integration: FEOL Challenges and Solutions
- Source :
- 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
- Publication Year :
- 2018
- Publisher :
- IEEE, 2018.
-
Abstract
- Scaling of high-performance logic devices is essentially driven by two requirements: Low leakage and high drive current. Here we investigate select issues and solutions: (i) Diffusion in nano-structures; (ii) SD/E doping requirements and their implications for doping solutions; (iii) Wrap-Around-Contact integration challenges. We do this by using a "virtual" fab, i.e. by employing Technology Computer Aided Design tools to mimic closely the processing and electrical testing in a real, physical fab, in particular explicitly modeling the doping processes such as implant and diffusion.
Details
- Database :
- OpenAIRE
- Journal :
- 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
- Accession number :
- edsair.doi...........8a4829e039685f31246cae7c13e60294