A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm/sup 2/ with 0.4 /spl mu/m CMOS technology.