Experimental investigation of an advanced static VAr compensator

An advanced static VAr compensator (ASVC) employing a three-level inverter is presented. The paper describes the operating principles and construction of a hardware model of this ASVC scheme. The performance of the ASVC is obtained from an experimental study carried out on the laboratory model. The use of the selective harmonic elimination modulation technique (SHEM) to minimise harmonics is explored. Experimental studies have been carried out to determine the effect of the DC-side capacitor on the harmonic performance of the scheme and the open-loop response speed is also evaluated. Finally, the economic feasibility of this scheme is briefly assessed by comparing the ASVC with a conventional thyristor-controlled reactor/fixed-capacitor scheme.