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Memory-efficient algorithms for the verification of temporal properties
- Source :
- CAV (DIMACS/AMS volume)
- Publication Year :
- 1992
- Publisher :
- Springer Science and Business Media LLC, 1992.
-
Abstract
- This article addresses the problem of designing memory-efficient algorithms for the verification of temporal properties of finite-state programs. Both the programs and their desired temporal properties are modeled as automata on infinite words (Buchi automata). Verification is then reduced to checking the emptiness of the automaton resulting from the product of the program and the property. This problem is usually solved by computing the strongly connected components of the graph representing the product automaton. Here, we present algorithms that solve the emptiness problem without explicitly constructing the strongly connected components of the product graph. By allowing the algorithms to err with some probability, we can implement them with a randomly accessed memory of size O(n) bits, where n is the number of states of the graph, instead of O(n log n) bits that the presently known algorithms require.
- Subjects :
- Model checking
Strongly connected component
Theoretical computer science
Computer science
Büchi automaton
Theoretical Computer Science
Automaton
Linear temporal logic
Hardware and Architecture
Graph (abstract data type)
Temporal logic
Algorithm
Time complexity
Computer Science::Formal Languages and Automata Theory
Software
Subjects
Details
- ISSN :
- 15728102 and 09259856
- Volume :
- 1
- Database :
- OpenAIRE
- Journal :
- Formal Methods in System Design
- Accession number :
- edsair.doi...........864019543c060315e98d01f9b24370b3
- Full Text :
- https://doi.org/10.1007/bf00121128