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Low-delay scheduling algorithm that considers fairness between ports

Authors :
Hirotada Kawakami
Koichi Asatani
Source :
Electronics and Communications in Japan (Part I: Communications). 90:43-52
Publication Year :
2007
Publisher :
Wiley, 2007.

Abstract

A Virtual Output Queuing (VOQ) input buffer type switch provided with a buffer in each input port is proposed in this paper as an input buffer type switch that avoids Head-of-Line (HoL) blocking. A scheduling algorithm for a multiple VOQ input buffer type switch is also proposed. As a representative algorithm we use a Two-Dimensional Round Robin (2DRR) scheduling algorithm that achieves low-delay and has iSLIP to avoid starvation as well as high fairness between ports. This paper also proposes a layered scheduling algorithm for a VOQ input buffer type switch with an objective of fairness between ports and switching with lower delay. The frequency of packets not being output is reduced regardless of whether an output port is empty by using up patterns of all I/O pairs in N input N output switches. The N input N output switching is divided into smaller units. Fairness between the units is achieved by successively shifting the order of priority of each unit that will be switched. Simulations were used to evaluate the effectiveness of the proposed scheduling algorithm. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 90(6): 43–52, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.20313

Details

ISSN :
15206424 and 87566621
Volume :
90
Database :
OpenAIRE
Journal :
Electronics and Communications in Japan (Part I: Communications)
Accession number :
edsair.doi...........83209cc467e017329d577f12f5ba046a
Full Text :
https://doi.org/10.1002/ecja.20313