RETRACTED ARTICLE: An energy-efficient reconfigurable accelerators in multi-core systems using PULP-NN

Emerging developments in embedded computer systems and applications demand low energy consumption and high performance. Owing to increased demand for low-voltage computing and lowered technology returns, academia and industry are interested primarily in energy-efficient accelerators. Hardware accelerators have the greatest disadvantage that they are not programmable. It can also be misused for a particular task. The number of accelerators in a device can cause scalability problems. Flexibility and scalability issues are present in programmable accelerators. Coarse-grained reconfigurable architecture (CGRA) design, implementation, computer systems integration and compilation for CGRA are the key contributions in this proposed design. First of all in parallel ultra-low-power processing system (PULP), the CGRA-based integrated programmable array (IPA) is implemented. Second, PULP-NN is a coding library that has been developed for the RISC-V cluster with parallel, high–low storage. The key development in PULP-NN is that the latest move towards aggressive quantization of deep neural network inferences which is a collection of kernels which use bytes and sub-byte information types up to INT-1. The library in the proposed procedure utilizes advanced sign handling expansions in the RISC-V PULP processors and in bunch matches, to accomplish ideal energy effectiveness of estimation execution.