A 3-stage Pseudo Single-phase Flip-flop family

MLA

Alfred Yeung, et al. “A 3-Stage Pseudo Single-Phase Flip-Flop Family.” 2012 Symposium on VLSI Circuits (VLSIC), June 2012. EBSCOhost, https://doi.org/10.1109/vlsic.2012.6243845.

APA

Alfred Yeung, Luca Ravezzi, Mark Horowitz, & Hamid Partovi. (2012). A 3-stage Pseudo Single-phase Flip-flop family. 2012 Symposium on VLSI Circuits (VLSIC). https://doi.org/10.1109/vlsic.2012.6243845

Chicago

Alfred Yeung, Luca Ravezzi, Mark Horowitz, and Hamid Partovi. 2012. “A 3-Stage Pseudo Single-Phase Flip-Flop Family.” 2012 Symposium on VLSI Circuits (VLSIC), June. doi:10.1109/vlsic.2012.6243845.