Features of Packaging Electronic Devices and Necessary Technological Requirements for Quality of Packaging

We studied the physical and technological features of packaging high integrated micro-assemblies, as well as multi-chip modules. Technological operations of packaging process test chips at the plate level by casting compound were carried out and the optimal conditions for their implementation were established. Sealing of chips at the wafer level was carried out using filling compounds Silterm-1B and Silterm-1K. As a result, using Silterm-1B compound with additives up to 10% of the total mass of finely dispersed silicon particles with a size not exceeding 5 μm, it was possible to reduce the thermal expansion coefficient of the entire multilayer structure to 50 * 10-6 1 / K, which subsequently reduced the deformation of the structure at high-temperature processes, and also increased the thermal conductivity of the structure.