Fail silent and robust power management architectures to enable autonomous driving embedded systems

This paper presents the latest functional safety innovations at the power management level of a System Basis Chip (SBC), from the development phase to system design, underscoring the link to reliability and how to enable hardware that is safety ready. The presentation will also demonstrate how using architecture developed for Automotive Safety Integrity Level (ASIL) can help improve the functional robustness of an embedded system with a destructive test performed on the Integrated Circuit (IC) The experimental results show the robustness of the safety architecture and how the safe state is activated in case of destruction by an Electrical Over Stress (EOS).