A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM

An integrated memory array processor (IMAP) LSI has peak performance of 3.84 GIPS and is suitable for high-speed, low-level image processing (LIP). Keys to performance are: integration of 64 simple processing elements (PEs) and 2 Mb SRAM with 128 b I/O, and single-instruction stream multiple-data stream (SIMD) parallel processing by use of 1.28 GB/s on-chip processor-memory bandwidth. A large number of active sense amplifiers ordinarily used in a wide memory bandwidth creates the problem of large power consumption. The number of active sense amplifiers here is reduced by a factor of 4 by accessing half of each word at a time, but accessing it at twice the speed of the PE clock. This keeps power consumption low. Each memory block can perform indexed addressing within its pages. This capability contributes to IMAP flexibility and efficiency in LIP. To raise yield, the architecture employs 4-way block replacement redundancy. IMAP is fabricated in 0.55 /spl mu/m BiCMOS 2-layer metal process technology. >