ESD-Immunity Influence of Ultra-high Voltage nLDMOS as the Drift Region Embedded a P-well

The influence of different embedded P-well lengths in drift region on ESD ability in ultra-high voltage LDMOS via a TSMC $0.5- \mu \mathrm {m}300 -\mathrm {V}$ process is investigated in this paper. By TLP and HBM testers, the corresponding trigger voltage, holding voltage, secondary breakdown current and HBM value of these DUTs can be obtained. Finally, after experimental analysis, the HBM value is higher than that of the reference DUT when the length of the P well is 5, 7, and $9 \mu \mathrm {m}$. And, compared with the reference DUT, as the length of the P well is $9 \mu \mathrm {m}$ which has a higher holding voltage upto 65.5-V (increased by 108%) and HBM value upto 5000-V (increased by 173%).