[Untitled]

A DDS type circuit structure for producing numerically programmable square wave clock signal is presented. The high speed D/A converter needed in conventional DDS systems is replaced by an N tap delay line time domain interpolator that effectively increases the sampling rate by a factor of N. Thus the circuit can be used up to full clock rate without image filtering. A prototype IC with clock frequency of 30 MHz, 5 bit interpolator and SFDR of −40 dBc up to 10 MHz and −33 dBc up to 15 MHz has been designed and tested.