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A single-chip MPEG2 video decoder LSI

Authors :
Tadahiro Oku
Takayasu Sakurai
Tatsuhiko Demura
Kazukuni Kitagaki
S. Ishiwata
Hiroyuki Hara
S. Michinaka
Takayoshi Shimazawa
Tomoo Yamakage
G. Otomo
Tetsu Nagamatsu
S. Suzuki
N. Goto
T. Oto
Katsuhiro Seta
Toshinori Odaka
K. Maeguchi
Yoshiharu Uetani
Masataka Matsui
Source :
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
Publication Year :
2002
Publisher :
IEEE, 2002.

Abstract

This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However, the processing speed should be more than four times faster than MPEG1. Moreover, several algorithms and structures to handle interlaced pictures are added to the MPEG1 standard. This LSI decodes in real time all motion-compensation modes and picture structures in MPEG2 bit streams of not only CCIR601 but also HDTV resolution. >

Details

Database :
OpenAIRE
Journal :
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
Accession number :
edsair.doi...........7176aebc1b6a53ed2eac1afba3ee930e