Régulation du flot d'instructions pour des processeurs orientés temps réel

The time predictability of the components of a real-time system is required whenever it must be guaranteed that deadlines will be met. Various techniques have been proposed to evaluate the Worst-Case Execution Time (WCET) of programs but current high-performance processors still cannot be safely modelled. We acknowledge the difficulty of taking into account more and more dynamic mechanisms within static analysis and this motivates the approach we propose here. The main idea is that the processor architecture should be adapted to fit WCET estimation techniques. We focus on dynamically-scheduled superscalar pipelines which have been proved unpredictable due to the possible temporal interactions between distant blocks. We propose to include a hardware mechanism that regulates the instruction flow so that subsequent basic blocks execute independently one of each other. This would allow any WCET estimation tool to consider only the individual execution times of the basic blocks.