FinFET based SRAMs in Sub-10nm domain

An exponential rise in transistor count, have increased the power consumption of the modern digital system. Moreover, at lower technology node, the performance of conventional CMOS designs degrades because of the short channel effects (SCEs). In sub-10 ​nm technologies, FinFET devices have good gate control and achieve superior performance than CMOS designs. FinFET devices possess high ION current and improved scalability compared to conventional CMOS. Among numerous double gate (DG) devices, the quasiplanar FinFET structure gained huge attention because of the simple fabrication process [4]. However, FinFET based designs have a major width quantization issue. The width of FinFET device varies only in quanta of silicon fin height (HFIN) [4]. This is a critical issue for ratioed designs like Static Random-Access Memory (SRAMs), where proper sizing of transistors is essential for correct functionality. With process variations, this issue becomes even worse and affect the performance of SRAM cell. The SRAM has a significant performance impact on current nanoelectronics systems. Next-generation devices overcome the short-channel effects (SCE) of CMOS technology and can be used to improve the efficiency of SRAM designs. FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain. The read stability and write ability of SRAM cells are determined using Static Noise Margin (butterfly) and N-curve methods. Moreover, this manuscript presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFET Based SRAM. In addition to this, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations to determine the robustness of SRAM designs. Simulations were done in HSPICE using 7 ​nm technology.