Cross link insertion for improving tolerance to variations in clock network synthesis

Cross links have been used to reduce skew variations in clock trees. In earlier studies cross links are inserted between the sinks of DC-connected trees. In this paper, we propose a link insertion scheme that inserts cross links between internal nodes of a clock tree. In addition to reducing the skew variability, the proposed approach also reduces the total cross link length. Our work also improves the correlation of sink delays for those sinks within a subtree that have similar path lengths to the cross link. Monte-Carlo (MC) simulations on the ISPD-2010 benchmarks showed that our work could handle variations effectively. In addition to meeting all the design constraints, the solutions produced by our approach have on the average 32% lower capacitance than the least capacitance obtained by the top three teams in the ISPD-2010 design contest [1].