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A microprocessor with a 128 b CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder

Authors :
K. Kutaragi
M. Suzuoki
T. Hiroi
H. Magoshi
S. Okamoto
M. Oka
A. Ohba
Y. Yamamoto
M. Furuhashi
M. Tanaka
T. Yutaka
T. Okada
M. Nagamatsu
Y. Urakawa
M. Funyu
A. Kunimatsu
H. Goto
K. Hashimoto
N. Ide
H. Murakami
Y. Ohtaguro
A. Aono
Source :
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
Publication Year :
2003
Publisher :
IEEE, 2003.

Details

Database :
OpenAIRE
Journal :
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)
Accession number :
edsair.doi...........6b4135bbb44a54691bddd7ac5e573b54
Full Text :
https://doi.org/10.1109/isscc.1999.759229