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Switched-capacitor simulation models for full-chips verification
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 11:1363-1371
- Publication Year :
- 1992
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 1992.
-
Abstract
- Models and techniques used in a switched-capacitor functional model generator are described. The simulation models described are asynchronous with respect to the clock inputs, and the proposed models are useful for achieving functional verification of chips consisting of clock generating circuitry, switched-capacitor circuits, and other analog or digital blocks. Graph-based methods are used for each clock configuration to minimize CPU requirements. Continuous feedthrough of the analog signals is adequately handled. The program MODGENSC has been developed to generate the models directly from the circuit description in SWITCAP. With this capability, full-chip mixed digital/analog simulation is achievable and the simulation time is reduced significantly. >
- Subjects :
- Digital electronics
Functional verification
business.industry
Computer science
Feedthrough
Digital clock manager
Filter (signal processing)
Integrated circuit
Switched capacitor
Computer Graphics and Computer-Aided Design
law.invention
Analog signal
Asynchronous communication
law
Electronic engineering
Electrical and Electronic Engineering
business
Software
Electronic circuit
Subjects
Details
- ISSN :
- 02780070
- Volume :
- 11
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........66c5093248fd1c2154daa54a0be62616