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A CMOS current-mode squaring circuit free of error resulting from carrier mobility reduction
- Source :
- Analog Integrated Circuits and Signal Processing. 81:23-28
- Publication Year :
- 2014
- Publisher :
- Springer Science and Business Media LLC, 2014.
-
Abstract
- This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation technique to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18 µm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.2 %; power consumption is 326 µW and bandwidth of 340 MHz.
- Subjects :
- Electron mobility
Engineering
Linearity error
business.industry
Bandwidth (signal processing)
Electrical engineering
Surfaces, Coatings and Films
CMOS
Hardware and Architecture
Power consumption
Signal Processing
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Current mode
business
Cmos process
Subjects
Details
- ISSN :
- 15731979 and 09251030
- Volume :
- 81
- Database :
- OpenAIRE
- Journal :
- Analog Integrated Circuits and Signal Processing
- Accession number :
- edsair.doi...........65aea184e7c43455e3ab1c5366b082e2