Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

Thin SiO2 layers were thermally grown onto cubic silicon carbide (3C‐SiC) heteroepitaxial layers of different surface roughness and with different types of near‐surface epitaxial defects. Localized dielectric breakdown (BD) was studied by electrically stressing the system using Conductive Atomic Force Microscopy (C‐AFM), which constitutes a means to directly and simultaneously observe localized dielectric failure as a function of stress time and surface morphology with nanoscale lateral resolution. The BD kinetics was evaluated by fitting the experimental failure ratios as a function of stress time to the failure probability described by Weibull statistics, in turn allowing to distinguish between defect‐induced (extrinsic) and intrinsic dielectric BD events. The results give useful information about how morphological features at the 3C‐SiC surface influence the BD generation in thermally grown oxides on this polytype.