A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1ns pp and 223.6ps rms , respectively with a multiplication factor of 1,024.